The present invention relates to memory devices and methods of manufacturing the same. More particularly, the present invention relates to phase-changeable memory devices and methods of manufacturing the same.
Currently available memory devices include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device and the like. Memory devices are generally classified as either volatile or non-volatile memory devices based on whether they keep or lose data when a current/power is not provided to the memory devices. When it is desired to maintain data when no current is being provided, a non-volatile memory device, in particular, a flash memory device, is widely used as a data-storing memory. However, as a flash memory device is typically not a random access memory device, a time required for reading/writing data to the flash memory may be longer than desired. As such, in some applications, a ferro-electric RAM, a magnetic RAM, a phase-changeable RAM (PRAM) or the like have been proposed as a next generation memory device.
The PRAM generally writes and reads data using a phase-changeable material that has a crystalline structure that may have its phase changed into an amorphous structure, typically by the application of heat. An example of a suitable phase-changeable material includes chalcogenides having germanium (Ge), stibium (Sb) and tellurium (Te). Examples of phase-changeable memory devices are described in U.S. Pat. Nos. 6,586,761, 6,649,928, 6,579,760 and 6,621,096.
In a unit cell of a phase-changeable memory device, a gate structure serving as a word line is generally formed on a semiconductor substrate. Source/drain regions are formed in portions of the semiconductor substrate at both sides of the gate structure. A lower wiring is electrically connected to one of the source/drain regions. A lower electrode is electrically connected to another of the source/drain regions. A phase-changeable layer pattern makes contact with the lower electrode. Upper electrodes are formed on the phase-changeable layer pattern. An upper wiring is connected between the upper electrodes.
A current is typically flowed into the phase-changeable layer pattern to provide heat to the phase-changeable layer pattern. The crystalline structure of the phase-changeable layer pattern is changed into the amorphous structure and vice versa in accordance with an amount and a provided time of the current so that a data “0” or “1” may be written in the cell.
A phase-changeable material may have a resistance that varies significantly based on the crystal structure of the phase-changeable material. Thus, when a current is provided to the phase-changeable material, the amount of the current flowing in the phase-changeable material may greatly vary depending on the crystal structure of the phase-changeable material. The data state of “0” or “1” in the cell may be read by detecting a difference between the amounts of the current that flow during a read operation.
In a phase-changeable memory device, although only a small amount of current may be provided to the phase-changeable layer pattern, it would still be desirable to rapidly change the crystal structure of the phase-changeable material. To facilitate heating and phase change, the phase-changeable layer pattern may be formed to limit/prevent heat loss. The loss of heat may generally mainly occur at the upper electrode. Thus, to suppress such a heat loss, forming the phase-changeable layer pattern to have a relatively high thickness may be desired.
However, when the phase-changeable layer pattern has a thick thickness, a region in which the crystalline structure of the phase-changeable material is changed into the amorphous structure and vice versa to program the data may be greatly widened. Therefore, because a large amount of current may then be required to sufficiently crystallize the phase-changeable layer pattern, it may be difficult to crystallize the phase-changeable material. The crystallized phase-changeable layer pattern having a thick thickness generally has a high resistance (generally referred to as a set resistance). When the crystallized phase-changeable layer pattern has a high set resistance, a difference between the set resistance of the crystallized phase-changeable layer pattern and a reset resistance of the amorphous phase-changeable layer pattern may be reduced, which may cause the data state to be more difficult to discriminated.